The present invention relates generally to phase interpolators and methods of using, same in applications, and more specifically relates to a phase interpolator that includes cross-coupled switches which are configured to swap inputs. The present invention also specifically relates to a method of using a phase interpolator in high-speed, low power applications.
In many applications, a clock recovery circuit is required to recover an embedded clock signal from an incoming data stream. The embedded clock signal which is extracted from the data stream is often referred to as the xe2x80x9crecovered clock.xe2x80x9d FIG. 1 illustrates typical waveforms of incoming data and a xe2x80x9crecovered clockxe2x80x9d.
Depending on the application, the clock recovery circuit can be implemented either as a phase-locked loop (PLL) or as delay-locked loop (DLL) (see, for example, Thomas H. Lee et al., xe2x80x9cA 2.5 V CMOS delay-locked loop for an 18 Mbit, 500 Megabyte/s DRAMxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1491-1496, December 1994). While a PLL 10 is illustrated in FIG. 2, a DLL 20 is illustrated in FIG. 3. A key component in either implementation is a delay cell. Specifically, as illustrated in FIG. 2, in a PLL 10, several delay cells 12 are connected in a closed loop 14 to form a voltage-controlled oscillator (VCO) 16. The oscillation frequency is controlled by adjusting a control voltage that is sent to the delay cells 12. As illustrated in FIG. 3, in a DLL 20, the VCO 16 is replaced by a variable delay line (VDL) 22. The VDL 22 included in a DLL 20 is similar to a VCO 16 which is included in a PLL 10 except the delay cells 12 are not wrapped around (i.e., there is no feedback 14 from the output of the last delay cell to the input of the first delay cell xe2x80x94compare FIG. 3 to FIG. 2). Both the VCO 16 and VDL 22 present disadvantages. The main disadvantage of a VCO 16 is its sensitivity to noise. Specifically, due to its closed-loop topology (i.e. as a result of the feedback 14), any noise coupled into the VCO 16 will circulate around the loop 14 and, depending on the time constant of the PLL 10, could take a long time to diminish. A VDL 22 avoids this problem because the output of the last delay cell is not looped back. However, the VDL 22 presents a different disadvantage. Because the total adjustable delay range of a VDL 22 is finite, the DLL 20 must be designed to operate within the delay range of its VDL 22. Designing the DLL as such can be a relatively difficult task since the delay range of a VDL depends on many variables, such as temperature.
In recent years, designers have attempted to replace VCO""s and VDL""s with a phase interpolator (see, for example, Lee et al., id.). As shown in FIG. 4, a phase interpolator generates a new clock phase (xe2x80x9cOutxe2x80x9d) which locates between two input clock phases (xcfx860 and xcfx861). A phase interpolator can be configured for analog control or digital control. A possible circuit implementation of a phase interpolator 30a with analog control is illustrated in FIG. 5, while a possible circuit implementation of a phase interpolator 30b with digital control is illustrated in FIG. 6. Unfortunately, phase interpolators which are used to replace VCO""s and VDL""s generally consume a lot of power and cannot be used in applications where the data rates are high.
It is an object of an embodiment of the present invention to provide a phase interpolator which can be used in applications where the data rates are high.
Another object of an embodiment of the present invention to provide a phase interpolator which does not consume a lot of power.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a phase interpolator which includes cross-coupled switches and is configured to receive a plurality of input clock phases and generate a new output clock phase based on the input clock phases which are selected. The cross-coupled switches receive the input clock phases and are controlled by selection inputs to select which input clock phases are used to generate the new output clock phase.
The phase interpolator may be configured to receive four clock phases, but preferably is configured to receive eight clock phases. Preferably, the phase interpolator includes eight cross-coupled switches, such as two sets of four cross-coupled switches. Preferably, each set of switches is controlled by a different selection input. Hence, a first selection input controls one set of four cross-coupled switches, and second selection input controls the other set of four cross-coupled switches. Preferably, each pair of switchesxe2x80x94wherein each pair includes a switch from each setxe2x80x94is configured to receive the same clock phase. Specifically, each pair may be configured to receive a given, pre-determined clock phase (if the phase interpolator is configured to receive four clock phases), or a selector device such as a multiplexer can be connected to each pair of switches such that a clock phase can be selected from a plurality of clock phases (such as where the phase interpolator is configured to receive eight clock phases). The phase interpolator may be configured for analog or digital control. In order to strobe data effectively, two phase interpolators may be provided, wherein each phase interpolator receives the same clock phases and is controlled by the same selection inputs.